This invention relates to an information processing system and, in particular, to an information processing system including an instruction processing unit which is operable under pipeline control.
An information processing system usually includes an instruction processing unit. Among other functions, the instruction processing unit processes, as successive current instructions, program instructions fetched successively from a memory device to judge whether the successive current instructions are operable instructions or inoperable instructions. The information processing system further comprises a bank of general registers assigned with register numbers, respectively. The general registers are used as operand registers and result registers. The operand registers are connected to the instruction processing unit and are indicated by the successive current instructions. The operand registers indicated by operable instructions hold current operands for the operable instructions. The result registers are connected to the instruction processing unit and are indicated by the operable instructions.
The information processing system further comprises a plurality of executing units. The executing units are called indicated executing units when the executing units are indicated by the operable instructions. The indicated executing units are connected to the operand registers through an operand supplying path and are connected to the result registers through a result delivering path. The indicated executing units are for successively executing, as executing instructions, the operable instructions for the current operands to successively store current results in the result registers. In order to use one of the current results as a result to be executed after execution of one of the executing instruction on an operand following the current operands, a bypass arrangement is connected to the operand supplying path and to the result delivering path. The above-mentioned one of the current results should be stored in one of the result registers equal to one of the operand registers that is indicated by one of the inoperable instructions. Responsive to an enable signal supplied from the instruction processing unit, the bypass arrangement bypasses the bank of general registers. Therefore, the instruction processing unit includes a bypass control circuit for controlling the bypass arrangement by the enable signal.
Such bypass control circuits are disclosed in the specification of U.S. Pat. No. 4,777,592 issued to Haruo Yano and in the specification of U.S. Pat. No. 4,683,547 issued to Richard D. DeGroot. According to Yano and DeGroot, the bypass control circuit carries out control of the bypass arrangement by comparison between the register numbers of the result registers indicated by the operable instructions with the register numbers of the operand registers indicated by the inoperable instructions. Therefore, the conventional bypass control circuit has the disadvantage that it is impossible to duly control the bypass arrangement when advanced execution of instructions is carried out, as will become clear as the description proceeds.